Invited Talks
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S. Saxena, "Phase-locked Loop," One Week AICTE Sponsored Short Term Course (STC) on Mechatronics: Integrated Technology for Intelligent Machines, IIT Madras, Mar. 18, 2022.
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S. Saxena, "Wireline communication: The backbone of data transfer," STMicroelectronics Pvt. Ltd., Greater Noida, Jan. 25, 2019.
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S. Saxena, "Phase Locked Loops," Short-term Course on High-Speed Communication Circuits, Indian Institute of Technology Guwahati, June 27, 2018.
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S. Saxena, "Recent trends in IC design and its applications," Keynote address at Faculty Development Program, Sasi Institute of Technology and Engineering, Andhra Pradesh, Apr. 16, 2018. (Organized by NIT Warangal under EICT Academy, Govt. of India).
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S. Saxena, "Design techniques in high speed serial links," Faculty Development Program, Sasi Institute of Technology and Engineering, Andhra Pradesh, Apr. 16, 2018. (Organized by NIT Warangal under EICT Academy, Govt. of India).
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S. Saxena, "Design and analysis of PLL for SoC," Faculty Development Program on Recent Trends in VLSI Technology, St. Vincent Pallotti College of Engineering and Technology, Nagpur, Dec. 4-8, 2017. (Organized by IIITDM Jabalpur under EICT Academy, Govt. of India).
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S. Saxena, “Wireline communication: the backbone of data transfer,” 23rd National Conference on Communications, IIT Madras, Mar. 2017.
Tutorials
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S. Saxena, and N. Krishnapura, “Architecture and circuits for fractional-N clock synthesis in wireline/wireless applications,” 32nd International Conference on VLSID, Jan. 2019.
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S. Saxena, and N. Krishnapura, “High-Speed Serial Links: Architectures and Circuits for Clock and Data Recovery (CDR),” 31st International Conference on VLSID, Jan. 2018.
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N. Krishnapura, and S. Saxena, “High speed serial links,” Global Foundries, Bengaluru, India, Mar. 29-31, 2017.
Short-Term Courses
PLLs: AICTE Sponsored Short Term Course on PLLs (17-22 Dec. 2018)