Patents
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Saurabh Saxena, Gautam R, Jaya Deepthi Bandarupalli, Injection Locked Clock Multiplier with Embedded Phase Interpolator, Indian Patent, 411893, Nov. 2022.
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Qadeer Khan and Saurabh Saxena, Multi-Phase Low Dropout Voltage Regulator, Indian Patent 383434, Dec. 2021.
Book Chapter
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S. Saxena and P. K. Hanumolu, “Digital clock and data recovery circuits,” In Phase-Locked
Frequency Generation and Clocking, Institution of Engineering and Technology (IET) Press,
pp. 495-524, 2020. Link
Journal Papers
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P. P. Kumar, P. H. Rao and S. Saxena, "Design and analysis of 0.5–2.0 GHz RF frontend subsystems for IEMI applications," in IEEE Transactions on Electromagnetic Compatibility, doi: 10.1109/TEMC.2024.3480975
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S. Sadhukhan, A. Thakkar, P. Kumar and S. Saxena, "A 5.4-7.4 GHz ultra-low jitter injection-locked frequency tripler with 3rd harmonic current boosting input buffer," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 71, no. 11, pp. 4693-4697, Nov. 2024, doi: 10.1109/TCSII.2024.3446728.
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J. Deepthi and S. Saxena,"A 6.7-3.6pJ/b 0.63-7.5Gb/s rapid on/off clock and data recovery with < 55ns turn-on time," in IEEE Solid-State Circuits Letters, vol. 7, pp. 14-17, 2024, doi: 10.1109/LSSC.2023.3337045.
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A. K. Bellamkonda, P. H. Rao and S. Saxena, “Intentional Electromagnetic Interference Reception in 0.5-2.0 GHz,” IEEE Transactions on Electromagnetic Compatibility, vol. 64, no. 6, pp. 2163-2169, Dec. 2022, doi: 10.1109/TEMC.2022.3205160.
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J. D. Bandarupalli and S. Saxena, “A 2.5-5.0GHz clock multiplier with 3.2-4.5mUI rms jitter and 0.98-1.06mW/GHz in 65nm CMOS,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 9, pp. 3714-3718, Sept. 2022, doi: 10.1109/TCSII.2022.3177885.
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Gautam R and S. Saxena, “A 1.12-1.91 mW/GHz 2.46-4.92 GHz cascaded clock multiplier in 65nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 57, no. 6, pp. 1700-1711, June 2022, doi: 10.1109/JSSC.2022.3149391.
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S. Saxena, “Wireline communication: the backbone of data transfer,” CSI Transactions on ICT, vol. 9, no. 2, pp. 1-10, June 2020, doi: 10.1007/s40012-020-00297-1.
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S. Mukherjee, A. Das, S. Seth, and S. Saxena, “An energy-efficient 3Gb/s PAM4 full-duplex transmitter with 2-tap feed forward equalizer,” IEEE Transactions on Circuits and Systems II:
Express Briefs, vol. 67, no. 5, pp. 916-920, May 2020, doi: 10.1109/TCSII.2020.2984567. -
J. D. Bandarupalli, G. R, and S. Saxena, “A reconfigurable 0.1-10Gb/s voltage-mode transmitter
with 0.2-1V output swing,” IEEE Solid-State Circuits Letters, vol. 2, no. 7, pp. 53-56, Jul. 2019,
doi: 10.1109/LSSC.2019.2935897. -
A. Elkholy, S. Saxena, G. Shu, A. Elshazly, and P. K. Hanumolu, “Low-jitter multi-output alldigital
clock generator using DTC-based open loop fractional dividers,” IEEE Journal of Solid-State Circuits, vol. 53, no. 6, pp. 1806-1817, Aug. 2018, doi: 10.1109/JSSC.2018.2817602. -
M. Talegaonkar, T. Anand, A. Elkholy, A. Elshazly, R. K. Nandwana, S. Saxena, B. Young, W. -S. Choi, and P. K. Hanumolu, “A 5 GHz digital fractional-N PLL using a 1-bit delta-sigma frequency-to-digital converter in 65 nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 52, no. 9, pp. 2306-2320, Aug. 2017, doi: 10.1109/JSSC.2017.2718670.
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S. Saxena, G. Shu, R. K. Nandwana, M. Talegaonkar, A. Elkholy, T. Anand, W. -S. Choi, and P.K. Hanumolu, “A 2.8 mW/Gb/s, 14 Gb/s Serial Link Transceiver,” IEEE Journal of Solid-State Circuits, vol. 52, no. 5, pp. 1399-1411, May 2017, doi: 10.1109/JSSC.2016.2645738.
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R. K. Nandwana, S. Saxena, A. Elshazly, K. Mayaram, and P. K. Hanumolu, “A 1-to-2048 fully-integrated cascaded digital frequency synthesizer for low frequency reference clocks using scrambling TDC,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 64, no. 2, pp. 283-295, Feb. 2017, doi: 10.1109/TCSI.2016.2609855.
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A. Elkholy, S. Saxena, R. K. Nandwana, A. Elshazly, and P. K. Hanumolu, “A 2.0-5.5 GHz wide
bandwidth ring-based digital fractional-N PLL with extended range multi-modulus divider,” IEEE
Journal of Solid-State Circuits, vol. 51, no. 8, pp. 1771-1784, Aug. 2016, doi: 10.1109/JSSC.2016.2557807. -
G. Shu, W. S. Choi, S. Saxena, T. Anand, A. Elshazly, and P. K. Hanumolu, “A 4-to-10.5-Gb/s continuous-rate digital clock and data recovery with automatic frequency acquisition,” IEEE Journal of Solid-State Circuits, vol. 51, no. 2, pp. 428-439, Feb. 2016, doi: 10.1109/JSSC.2015.2497963.
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T. Anand, M. Talegaonkar, A. Elkholy, S. Saxena, A. Elshazly, and P. K. Hanumolu, “A 7Gb/s embedded clock transceiver for energy proportional links,” IEEE Journal of Solid-State Circuits, vol. 50, no. 12, pp. 3101-3119, Dec. 2015, doi: 10.1109/JSSC.2015.2470553.
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R. K. Nandwana, T. Anand, S. Saxena, S. –J. Kim, M. Talegaonkar, A. Elkholy, W. –S. Choi, A. Elshazly, and P. K. Hanumolu, “A calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolation method,” IEEE Journal of Solid-State Circuits, vol. 50, no. 4, pp. 882-895, April. 2015, doi: 10.1109/JSSC.2014.2385756.
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S. Saxena, R. K. Nandwana, and P. K. Hanumolu, “A 5Gb/s energy-efficient voltage-mode transmitter using time-based de-emphasis,” IEEE Journal of Solid-State Circuits, vol. 49, no. 8,
pp. 1827-1836, Aug. 2014, doi: 10.1109/JSSC.2014.2317142. -
G. Shu, S. Saxena, W. -S. Choi, M. Talegaonkar, A. Elshazly, B. Young, and P. K. Hanumolu, “A reference-less clock and data recovery circuit using phase-rotating phase-locked loop,” IEEE Journal of Solid-State Circuits, vol. 49, no. 4, pp. 1036-1047, April. 2014, doi: 10.1109/JSSC.2013.2296152.
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R. Zanbaghi, S. Saxena, G. C. Temes, and T. S. Fiez, “A 75-dB SNDR, 5-MHz bandwidth stage-shared 2-2 MASH delta-sigma modulator dissipating 16mW power,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 59, no. 8, pp. 1614-1625, Aug. 2012, doi: 10.1109/TCSI.2012.2206509.
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S. Z. Asl, S. Saxena, P. K. Hanumolu, K. Mayaram, and T. S. Fiez, “A 12.5-bit 4MHz 13.8mW
MASH delta-sigma modulator with multirated VCO-based ADC,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 59, no. 8, pp. 1604-1613, Aug. 2012, doi: 10.1109/TCSI.2012.2206506.
Conference Papers
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A. K. Bellamkonda, and S. Saxena, “A 1-28 dB attenuator loaded 0.5-2.0GHz receiver front-end detecting IEMI signals in 65 nm CMOS,” 2024 31st IEEE International Conference on Electronics, Circuits and Systems, Nancy, France (Accepted).
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J. Kim, R. Islam, J. M. L. Miller, J. Zhao, G. Vukasin, R. Kwon, S. Saxena, P. K. Hanumolu, T. W. Kenny, G. Bahl, “Fully differential gyrator using a dynamically biased 20MHz Lame mode resonator,” 2024 IEEE 37th International Conference on Micro Electro Mechanical Systems (MEMS).
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J. Deepthi and S. Saxena, "A 0.49-9.8 Gb/s 0.1-1V Output Swing Transmitter with 38.4MHz Reference and <30 ns Turn-On Time," ESSCIRC 2023 - IEEE 49th European Solid State Circuits Conference (ESSCIRC), Lisbon, Portugal, 2023, pp. 173-176, doi:10.1109/ESSCIRC59616.2023. 10268760.
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S. Nigam, M. Murali, H. S. Gupta and S. Saxena, “A 105-525MHz Integer-N Phase-Locked Loop in indigenous SCL 180nm CMOS,” 2023 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems (VLSID), Hyderabad, India, 2023, pp. 348-352, doi: 10.1109/VLSID57277.2023.00076. (Best Poster Award)
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S. Jakkoju, D. J. Bandarupalli, A. Srikanth, S. Thomas and S. Saxena, “A 2.25 GHz PLL with 0.05-2 MHz Inloop Phase Modulation and -70 dBc Reference Spur for Telemetry Applications,” 2023 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems (VLSID), Hyderabad, India, 2023, pp. 1-5, doi: 10.1109/VLSID57277.2023.00031.
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S. Sadhukhan, P. Kumar, A. Thakkar, A. Bhatia and S. Saxena, “A Class-C Injection-Locked Tripler with 48 dB Sub-Harmonic Suppression and 15 fs Additive RMS Jitter in 0.13μm BiCMOS Process,” 2022 IEEE International Symposium on Circuits and Systems (ISCAS), Austin, TX, USA, 2022, pp. 2740-2744, doi: 10.1109/ISCAS48785.2022.9937530.
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S. Mukherjee, S. Seth and S. Saxena, “A 5-Gb/s PAM4 Voltage Mode Transmitter with Current Mode Continuous Time Linear Equalizer,” 2022 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems (VLSID), Bangalore, India, 2022, pp. 1-5, doi: 10.1109/VLSID2022.2022.00013. (Naresh Malipeddy Honorable Mention Award)
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R. Gautam, J. D. Bandarupalli and S. Saxena, “A 2.5–5GHz Injection-Locked Clock Multiplier with Embedded Phase Interpolator in 65nm CMOS,” 2020 IEEE International Symposium on Circuits and Systems (ISCAS), Seville, Spain, 2020, pp. 1-5, doi: 10.1109/ISCAS45731.2020.9180829.
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Q. A. Khan, S. Saxena and A. Santra, “Area and current efficient capacitor-less low drop-out regulator using time-based error amplifier,” 2018 IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, 2018, pp. 1-5, doi: 10.1109/ISCAS.2018.8351598.
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R. K. Nandwana, S. Saxena, A. Elkholy, M. Talegaonkar, J. Zhu, W. S. Choi, A. Elmallah, and P. K. Hanumolu, “A 3-to-10Gb/s 5.75pJ/bit transceiver with flexible clocking in 65nm CMOS,” 2017 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2017, pp. 492-493, doi: 10.1109/ISSCC.2017.7870476.
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G. Shu, W. S. Choi, S. Saxena, S. -J. Kim, M. Talegaonkar, R. Nandwana, and P. K. Hanumolu, “A 16Mb/s-8Gb/s, 14.1-7.2pJ/bit source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS,” 2016 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2016, pp. 398-399, doi: 10.1109/ISSCC.2016.7418075.
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A. Elkholy, S. Saxena, and P. K. Hanumolu, “A 4mW wide bandwidth ring-based fractional-N DPLL with 1.9psrms integrated-jitter,” 2015 IEEE Custom Integrated Circuits Conference (CICC), San Jose, CA, USA, 2015, pp. 1-4, doi: 10.1109/CICC.2015.7338376.
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S. Saxena, G. Shu, R. K. Nandwana, M. Talegaonkar, A. Elkholy, T. Anand, S. -J. Kim, W. -S. Choi, and P. K. Hanumolu, “A 2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS,” 2015 IEEE Symposium on VLSI Circuits (VLSI Circuits), Kyoto, Japan, 2015, pp. C352-C353, doi: 10.1109/VLSIC.2015.7231320.
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T. Anand, M. Talegaonkar, A. Elkholy, S. Saxena, A. Elshazly, and P. K. Hanumolu, “A 7Gb/s rapid on/off embedded-clock serial-link transceiver with 20ns power-on time, 740µW off-state power for energy proportional links in 65nm CMOS,” 2015 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2015, pp. 1-3, doi: 10.1109/ISSCC.2015.7062927.
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R. K. Nandwana, T. Anand, S. Saxena, S. -J. Kim, M. Talegaonkar, A. Elkholy, W. -S. Choi, A. Elshazly, and P. K. Hanumolu, “A 4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement,” 2014 IEEE Symposium on VLSI Circuits, Honolulu, HI, USA, 2014, pp. 1-2, doi: 10.1109/VLSIC.2014.6858446.
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M. Talegaonkar, T. Anand, A. Elkholy, A. Elshazly, R. K. Nandwana, S. Saxena, B. Young, W. -S. Choi, and P. K. Hanumolu, “A 4.4-5.4GHz digital fractional-N PLL using sigma-delta frequency-to-digital converter,” 2014 Symposium on VLSI Circuits, Honolulu, HI, USA, 2014, pp. 1-2, doi: 10.1109/VLSIC.2014.6858392.
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A. Elkholy, A. Elshazly, S. Saxena, G. Shu, and P. K. Hanumolu, “A 20-to-1000MHz 14ps peak-to-peak jitter reconfigurable multi-output all-digital clock generator using open-loop fractional dividers in 65nm CMOS,” 2014 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2014, pp. 272-273, doi: 10.1109/ISSCC.2014.6757431.
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G. Shu, W. S. Choi, S. Saxena, T. Anand, A. Elshazly, and P. K. Hanumolu, “A 4-to-10.5Gb/s 2.2mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS,” 2014 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2014, pp. 150-151, doi: 10.1109/ISSCC.2014.6757377.
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S. Saxena, R. K. Nandwana, and P. K. Hanumolu, “A 5Gb/s 3.2mW/Gb/s 28dB loss-compensating pulse-width modulated voltage-mode transmitter,” 2013 IEEE Custom Integrated Circuits Conference (CICC), San Jose, CA, USA, 2013, pp. 1-4, doi: 10.1109/CICC.2013.6658403.
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R. K. Nandwana, S. Saxena, and P. K. Hanumolu, “A 2.5GHz 5.4mW 1-to-2048 digital clock multiplier using a scrambling TDC,” 2013 IEEE Symposium on VLSI Circuits, Kyoto, Japan, 2013, pp. C156-C157.
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G. Shu, S. Saxena, W. S. Choi, M. Talegaonkar, R. Inti, A. Elshazly, B. Young, and P. K. Hanumolu, “A 5Gb/s 2.6mW/Gb/s reference-less half-rate PRPLL-based digital CDR,” 2013 IEEE Symposium on VLSI Circuits, Kyoto, Japan, 2013, pp. C278-C279.
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R. Zanbaghi, S. Saxena, G. C. Temes, and T. S. Fiez, “A 75dB SNDR, 10MHz conversion bandwidth stage-shared 2-2 MASH sigma-delta modulator dissipating 9mW,” 2011 IEEE Custom Integrated Circuits Conference (CICC), San Jose, CA, USA, 2011, pp. 1-4, doi: 10.1109/CICC.2011.6055287.
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S. Z. Asl, S. Saxena, P. K. Hanumolu, K. Mayaram, and T. S. Fiez, “A 77dB SNDR, 4MHz MASH sigma-delta modulator with a second-stage multi-rate VCO-based quantizer,” 2011 IEEE Custom Integrated Circuits Conference (CICC), San Jose, CA, USA, 2011, pp. 1-4, doi: 10.1109/CICC.2011.6055290.
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S. Saxena, P. Sankar, and S. Pavan, “Automatic tuning of time constants in single-bit continuous-time delta-sigma modulators,” 2009 IEEE International Symposium on Circuits and Systems (ISCAS), Taipei, Taiwan, 2009, pp. 2257-2260, doi: 10.1109/ISCAS.2009.5118248.